Operation; Non-Maskable Interrupt Servicing - NEC V850/SB1 User Manual

5.2.1 Operation

If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the
handler routine.
(1) Saves the restored PC to FEPC.
(2) Saves the current PSW to FEPSW.
(3) Writes exception codes 0010H and 0020H to the higher halfword (FECC) of ECR.
(4) Sets the NP and ID bits of the PSW and clears the EP bit.
(5) Loads the handler address (00000010H, 00000020H) of the non-maskable interrupt routine to the PC, and
transfers control.
INTC accepted
CPU processing
150
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-1. Non-Maskable Interrupt Servicing
NMI input
Non-maskable interrupt request
PSW. NP
0
FEPC Restored PC
FEPSW PSW
ECR. FECC Exception code
PSW. NP 1
PSW. EP 0
PSW. ID 1
PC 00000010H,
00000020H
Interrupt servicing
User's Manual U13850EJ6V0UD
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Interrupt request pending