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(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICn).
2
An I
C interrupt is generated following either of two triggers.
• Eighth or ninth clock of the serial clock (set by WTIMn bit)
• Interrupt request generated when a stop condition is detected (set by SPIEn bit)
Remarks 1. n = 0, 1
2. WTIMn bit: Bit 3 of IIC control register n (IICCn)
SPIEn bit:
(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCLn pin from a sampling clock (n = 0, 1).
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK output circuit, stop condition detector, start condition detector, and ACK detector
These circuits are used to output and detect various control signals.
(11) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(12) Start condition generator
This circuit generates a start condition when the STTn bit is set.
However, in the communication reservation disabled status (IICRSVn = 1), when the bus is not released
(IICBSYn = 1), start condition requests are ignored and the STCFn bit is set.
Remark
IICRSVn bit: Bit 0 of IIC flag register n (IICFn)
IICBSYn bit: Bit 6 of IIC flag register n (IICFn)
STCFn bit:
(13) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCENn bit.
Remark
STCENn bit: Bit 1 of IIC flag register n (IICFn)
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CHAPTER 10
SERIAL INTERFACE FUNCTION
Bit 4 of IIC control register n (IICCn)
Bit 7 of IIC flag register n (IICFn)
User's Manual U13850EJ6V0UD
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