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10.4.15 Timing of data communication
2
When using I
C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn))
that specifies the data transfer direction and then starts serial communication with the slave device.
IIC bus shift register n (IICn)'s shift operation is synchronized with the falling edge of the serial clock (SCLn). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDAn pin.
Data input via the SDAn pin is captured by IICn at the rising edge of SCLn.
The data communication timing is shown below.
Remark
n = 0, 1
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CHAPTER 10
SERIAL INTERFACE FUNCTION
User's Manual U13850EJ6V0UD
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