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(f) Clock generator (CG)
The clock generator includes two types of oscillators; each for main clock (f
generates five types of clocks (f
clock for the CPU (f
CPU
(g) Timer/counter
A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8-
bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as
programmable pulse output.
The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit
timer.
The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit
timer.
(h) Watch timer
This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz
subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the
main clock.
(i) Watchdog timer
A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an
overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM)
after an overflow occurs.
(j) Serial interface (SIO)
The V850/SB2 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0,
UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4).
2
These plus the I
C bus interfaces (I
switchable between the UART and CSI and another two switchable between CSI and I
For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins.
For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins.
For CSI4, data is transferred via the SO4, SI4, and SCK4 pins.
2
2
For I
C0 and I
C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins.
C1 are equipped only in the µ PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY,
2
2
I
C0 and I
70F3036HY, and 70F3037HY.
For UART and CSI4, a dedicated baud rate generator is equipped.
(k) A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses
the successive approximation method.
(l) DMA controller
A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
CHAPTER 1
INTRODUCTION
, f
/2, f
/4, f
XX
XX
XX
XX
).
2
2
C0, I
C1) comprise five channels. Two of these channels are
User's Manual U13850EJ6V0UD
/8, and f
), and supplies one of them as the operating
XT
) and for subclock (f
),
XX
XT
2
C.
71
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