(10)IEBus slave status register (SSR)
This register indicates the communication status of the slave unit. After receiving a slave status transmission
request from the master, the CPU reads this register, and writes a slave status to the IEBus data register
(DR) to transmit the slave status. At this time, the telegraph length is automatically set to "01H" that setting of
the IEBus telegraph length register (DLR) is not required (because it is preset by hardware).
Bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to "01H" (mode 1).
After reset: 41H
SSR
STATSLV
STATLOCK
STATRX
STATTX
(a) Slave transmission status flag (STATSLV)...Bit 4
Reflects the contents of slave transmission enable flag.
(b) Lock status flag (STATLOCK)...Bit 2
Reflects the contents of locked flag.
(c) DR reception status (STATRX)...Bit 1
This flag indicates the DR reception state.
(d) DR transmission status (STATTX)...Bit 0
This flag indicates the DR transmission state.
580
CHAPTER 19
IEBus CONTROLLER (V850/SB2)
R
Address: FFFFF3F2H
7
6
5
0
1
0
STATSLV
0
Slave transmission stops
1
Slave transmission enabled
0
Unlock status
1
Lock status
0
Receiving data not stored in DR
1
Receiving data stored in DR
0
Transmission data not stored in DR
1
Transmission data stored in DR
User's Manual U13850EJ6V0UD
<4>
3
<2>
STATLOCK STATRX
0
Slave transmission status flag
Lock status flag
DR receive status
DR transmit status
<1>
<0>
STATTX