Bus Hold Timing - NEC V850/SB1 User Manual

CLKOUT (output)
HLDRQ (input)
HLDAK (output)
A16 to A21 (output)
A1 to A15 (output)
AD0 to AD15 (I/O)
Address
ASTB (output)
R/W (output)
DSTB, RD,
WRH, WRL (output)
UBEN, LBEN (output)
WAIT (input)
Notes 1. If the HLDRQ signal is inactive (high level) at this sampling timing, the bus hold state is not entered.
2. If the bus hold status is entered after a write cycle, a high level may be output momentarily from the
R/W pin immediately before the HLDAK signal changes from high level to low level.
Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken line indicates the high-impedance state.
CHAPTER 4 BUS CONTROL FUNCTION
Figure 4-10. Bus Hold Timing
T2 T3 TH
Note 1
Address
Data
User's Manual U13850EJ6V0UD
TH TH TH
Address
Note 2
TI T1
Address
Address
Undefined
Address
143