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(5) P40 to P47 (Port 4) ··· 3-state I/O
P40 to P47 constitute an 8-bit I/O port that can be set to input or output pins in 1-bit units.
P40 to P47 can also function as a time division address/data bus (AD0 to AD7) when memory is expanded
externally.
The I/O signal level uses the bus interface power supply pins BV
(a) Port function
P40 to P47 can be set to input or output in 1-bit units using the port 4 mode register (PM4).
(b) Alternate functions (External expansion function)
P40 to P47 can be set as AD0 to AD7 using the memory expansion mode register (MM).
(i)
AD0 to AD7 (Address/data bus 0 to 7) ··· 3-state I/O
These comprise a multiplexed address/data bus that is used for external access. At the address timing
(T1 state), these pins operate as AD0 to AD7 (22-bit address) output pins. At the data timing (T2, TW,
T3), they operate as the lower 8-bit I/O bus pins for 16-bit data. The output changes in synchronization
with the rising edge of the clock in each state within the bus cycle. When the timing sets the bus cycle
to inactive, these pins go into a high-impedance state.
(6) P50 to P57 (Port 5) ··· 3-state I/O
P50 to P57 constitute an 8-bit I/O port that can be set to input or output in 1-bit units.
P50 to P57 can also function as I/O port pins and as a time division address/data buses (AD8 to AD15) when
memory is expanded externally.
The I/O signal level uses the bus interface power supply pins BV
(a) Port function
P50 to P57 can be set to input or output in 1-bit units using the port 5 mode register (PM5).
(b) Alternate functions (External expansion function)
P50 to P57 can be set as AD8 to AD15 using the memory expansion mode register (MM).
(i)
AD8 to AD15 (Address/data bus 8 to 15) ··· 3-state I/O
These comprise a multiplexed address/data bus that is used for external access. At the address timing
(T1 state), these pins operate as AD8 to AD15 (22-bit address) output pins. At the data timing (T2, TW,
T3), they operate as the higher 8-bit I/O bus pins for 16-bit data.
synchronization with the rising edge of the clock in each state within the bus cycle. When the timing
sets the bus cycle to inactive, these pins go into a high-impedance state.
CHAPTER 2
PIN FUNCTIONS
User's Manual U13850EJ6V0UD
and BV
as a reference.
DD
SS
and BV
as reference.
DD
SS
The output changes in
85
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