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SCLn
SCLn inversion
The selection clock is set using a combination of the SMCn, CLn1, and CLn0 bits of IIC clock selection register
n (IICCLn), the CLXn bit of IIC function expansion register n (IICXn), and IICCEn1 and the IICCEn0 bits of IIC
clock expansion register n (IICCEn) (n = 0, 1).
IICCEn
IICXn
IICCLn
Bit 1
Bit 0
Bit 0
Bit 3
Bit 1
IICCEn1 IICCEn0
CLXn
SMCn
CLn1
x
x
1
1
x
x
0
1
x
x
0
1
0
1
0
1
1
0
0
1
0
0
0
1
x
x
0
0
x
x
0
0
x
x
0
0
0
1
0
0
1
0
0
0
0
0
0
0
Other than above
Note This cannot be set in the µ PD703034BY, 703035BY, and 70F3035BY.
Remarks 1. n = 0, 1
2. x: don't care
3. When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and
P27/TO3/TI3 pins in the timer output mode.
CHAPTER 10
SERIAL INTERFACE FUNCTION
m x T + t
R
t
m/2 x T
R
SCLn inversion
Table 10-9. Selection Clock Setting
Selection Clock
(f
/m)
XX
Bit 0
CLn0
0
x
f
/12
XX
0
x
f
/24
XX
1
0
f
/48
XX
1
1
f
/36
XX
1
1
f
/54
XX
1
1
n = 0
TM2 output/18
n = 1
TM3 output/18
0
0
f
/44
XX
0
1
f
/86
XX
1
0
f
/172
XX
1
1
f
/132
XX
1
1
f
/198
XX
1
1
n = 0
TM2 output/66
n = 1
TM3 output/66
Setting prohibited
User's Manual U13850EJ6V0UD
+ t
F
t
m/2 x T
F
SCLn inversion
Settable Main Clock Frequency (f
Range
4.0 MHz to 4.19 MHz
4.0 MHz to 8.38 MHz
8.0 MHz to 16.67 MHz
12.0 MHz to 13.4 MHz
Note
16.0 MHz to 20.0 MHz
TM2 setting
TM3 setting
2.0 MHz to 4.19 MHz
4.19 MHz to 8.38 MHz
8.38 MHz to 16.67 MHz
12.0 MHz to 13.4 MHz
Note
16.0 MHz to 20.0 MHz
TM2 setting
TM3 setting
)
Operation Mode
XX
High-speed mode
(SMCn = 1)
Normal mode
(SMCn = 0)
351
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