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(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel
shifter (32 bits) help accelerate processing of complex instructions.
(b) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory space and the CPU does not send a bus cycle
start request, the BCU generates a prefetch address and prefetches the instruction code.
prefetched instruction code is stored in an instruction queue.
(c) ROM
This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.
The ROM capacity varies depending on the product. The ROM capacity of each product is shown
below.
µ PD703031B, 703031BY:
µ PD703033B, 703033BY:
µ PD70F3033B, 70F3033BY: 256 KB (flash memory)
µ PD703030B, 703030BY:
µ PD70F3030B, 70F3030BY: 384 KB (flash memory)
µ PD703032B, 703032BY:
µ PD70F3032B, 70F3032BY: 512 KB (flash memory)
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each
product is shown below.
µ PD703031B, 703031BY:
µ PD703033B, 703033BY, 70F3033B, 70F3033BY: 16 KB (mapping starts at FFFFB000H)
µ PD703030B, 703030BY, 70F3030B, 70F3030BY,
703032B, 703032BY, 70F3032B, 70F3032BY:
RAM can be accessed by the CPU in one clock cycle during data access.
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed for interrupt sources.
50
CHAPTER 1
INTRODUCTION
128 KB (mask ROM)
256 KB (mask ROM)
384 KB (mask ROM)
512 KB (mask ROM)
8 KB (mapping starts at FFFFD000H)
24 KB (mapping starts at FFFF9000H)
User's Manual U13850EJ6V0UD
The
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