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2.2 Pin States
The operating states of various pins are described below with reference to their operating modes.
Operating State
Pin
AD0 to AD15
A1 to A15
A16 to A21
LBEN, UBEN
R/W
DSTB, WRL, WRH, RD
ASTB
HLDRQ
HLDAK
WAIT
CLKOUT
Notes 1.
Pins (except the CLKOUT pin) are used as port pins (input mode) after reset.
2.
The bus cycle inactivation timing occurs when the internal memory area is specified by the program
counter (PC) in the external expansion mode.
• When the external memory area has not been accessed even once after reset is released and the
3.
external expansion mode is set: Undefined
• When the bus cycle is inactivated after access to the external memory area, or when the external
memory area has not been accessed even once after the external expansion mode is released and
set again: The state of the external bus cycle when the external memory area accessed last is held.
4.
Low level (L) when in clock output inhibit mode
Remark Hi-Z: High impedance
Held: State is held during preset external bus cycle
L:
Low-level output
H:
High-level output
−:
Input without sampling sampled (not acknowledged)
80
CHAPTER 2
Table 2-3. Operating States of Pins in Each Operating Mode
Note 1
Reset
HALT Mode/
Idle State
Hi-Z
Hi-Z
Hi-Z
Held
Hi-Z
Held
Hi-Z
Held
Hi-Z
Hi-Z
Hi-Z
—
Operating
Hi-Z
Operating
—
Hi-Z
Operating
User's Manual U13850EJ6V0UD
PIN FUNCTIONS
IDLE Mode/
STOP Mode
Hi-Z
Held
Hi-Z
Hi-Z
H
Hi-Z
H
Hi-Z
H
Hi-Z
—
Hi-Z
—
—
Note 4
L
Bus Hold
Bus Cycle
Note 2
Inactive
Hi-Z
Hi-Z
Note 3
Held
Held
Note 3
Hi-Z
Held
Note 3
Hi-Z
Held
Hi-Z
H
Hi-Z
H
Hi-Z
H
Operating
Operating
L
Operating
—
—
Note 4
Note 4
Operating
Operating
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