NEC V850/SB1 User Manual page 160

32-bit single-chip microcontroller
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Main routine
EI
Interrupt request i
(level 2)
Interrupt request l
Interrupt request n
(level 2)
Interrupt request o
Interrupt
(level 3)
request p
(level 2)
Interrupt request s
Interrupt request u
(level 1)
Notes 1.
Lower default priority
2.
Higher default priority
160
CHAPTER 5
INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-6. Example of Multiple Interrupt Servicing (2/2)
Servicing of i
EI
Interrupt
request j
(level 3)
Interrupt request k
(level 1)
Servicing of j
Servicing of l
Interrupt
request m
(level 3)
(level 1)
Servicing of n
Servicing of m
Servicing of o
Servicing of p
EI
EI
Interrupt
request q
Interrupt
(level 1)
request r
(level 0)
Servicing of s
Interrupt
request t
Note 1
(level 2)
Note 2
(level 2)
Servicing of u
Servicing of t
User's Manual U13850EJ6V0UD
Processing of k
Interrupt request j is held pending because its
priority is lower than that of i. k that occurs after j
is acknowledged because it has the higher priority.
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt requests n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Servicing of q
Servicing of r
EI
EI
If levels 3 to 0 are acknowledged
Pending interrupt requests t and u are
acknowledged after processing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.

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