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10.3.1 Configuration
2
I
Cn includes the following hardware (n = 0, 1).
Registers
Control registers
(1)
IIC shift registers 0 and 1 (IIC0, IIC1)
IICn is used to convert 8-bit serial data into 8-bit parallel data and vice versa. IICn can be used for both
transmission and reception (n = 0, 1).
Write and read operations to IICn are used to control the actual transmit and receive operations.
IICn is set by an 8-bit memory manipulation instruction.
RESET input clears IIC0 and IIC1 to 00H.
(2)
Slave address registers 0 and 1 (SVA0, SVA1)
SVAn sets local addresses when in slave mode.
SVAn is set by an 8-bit memory manipulation instruction (n = 0, 1).
RESET input clears SVA0 and SVA1 to 00H.
(3)
SO latch
The SO latch is used to retain the SDAn pin's output level (n = 0, 1).
(4)
Wakeup controller
This circuit generates an interrupt request when the address received by this register matches the address
value set to slave address register n (SVAn) or when an extension code is received (n = 0, 1).
(5)
Clock selector
This selects the sampling clock to be used.
(6)
Serial clock counter
This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive
operations and is used to verify that 8-bit data was sent or received.
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CHAPTER 10
SERIAL INTERFACE FUNCTION
Table 10-2. Configuration of I
Item
IIC shift registers 0 and 1 (IIC0, IIC1)
Slave address registers 0 and 1 (SVA0, SVA1)
IIC control registers 0 and 1 (IICC0, IICC1)
IIC status registers 0 and 1 (IICS0, IICS1)
IIC clock selection registers 0 and 1 (IICCL0, IICCL1)
IIC clock expansion registers 0 and 1 (IICCE0, IICCE1)
IICC function expansion registers 0 and 1 (IICX0, IICX1)
User's Manual U13850EJ6V0UD
2
Cn
Configuration
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