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(7) IIC shift registers 0, 1 (IIC0, IIC1)
IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can
be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0, 1).
After reset: 00H
7
IICn
(n = 0, 1)
(8) Slave address registers 0, 1 (SVA0, SVA1)
2
SVAn holds the I
C bus's slave addresses.
It can be read from or written to in 8-bit units, but bit 0 should be fixed to 0.
After reset: 00H
7
SVAn
(n = 0, 1)
2
10.3.3
I
C bus mode functions
(1)
Pin configuration
The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows (n = 0, 1).
SCLn .............. This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
SDAn .............. This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-
up resistor is required.
CHAPTER 10
SERIAL INTERFACE FUNCTION
R/W
Address: FFFFF348H, FFFFF358H
6
5
4
R/W
Address: FFFFF346H, FFFFF356H
6
5
4
User's Manual U13850EJ6V0UD
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