NEC V850/SB1 User Manual page 21

32-bit single-chip microcontroller
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Figure No.
5-13
Pipeline Operation at Interrupt Request Acknowledgment........................................................................... 177
5-14
Pipeline Flow and Interrupt Request Signal Generation Timing................................................................... 179
5-15
Key Return Block Diagram ........................................................................................................................... 181
6-1
Clock Generator ........................................................................................................................................... 183
6-2
Oscillation Stabilization Time ....................................................................................................................... 196
7-1
Block Diagram of TM0 and TM1................................................................................................................... 201
7-2
Control Register Settings When TMn Operates as Interval Timer ............................................................... 211
7-3
Configuration of Interval Timer ..................................................................................................................... 212
7-4
Timing of Interval Timer Operation ............................................................................................................... 212
7-5
Control Register Settings in PPG Output Operation..................................................................................... 213
7-6
Configuration of PPG Output........................................................................................................................ 214
7-7
PPG Output Operation Timing...................................................................................................................... 214
7-8
Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register............................................................................................................................ 215
7-9
Configuration for Pulse Width Measurement with Free-Running Counter.................................................... 216
7-10
Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register
(with Both Edges Specified) ......................................................................................................................... 216
7-11
Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter.................... 217
7-12
CRn1 Capture Operation with Rising Edge Specified .................................................................................. 218
7-13
Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified) .................. 218
7-14
Control Register Settings for Pulse Width Measurement with Free-Running Counter
and Two Capture Registers.......................................................................................................................... 219
7-15
Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers
(with Rising Edge Specified)......................................................................................................................... 220
7-16
Control Register Settings for Pulse Width Measurement by Restarting ....................................................... 221
7-17
Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) ....................................... 221
7-18
Control Register Settings in External Event Counter Mode.......................................................................... 222
7-19
Configuration of External Event Counter ...................................................................................................... 223
7-20
Timing of External Event Counter Operation (with Rising Edge Specified).................................................. 223
7-21
Control Register Settings in Square Wave Output Mode ............................................................................. 224
7-22
Timing of Square Wave Output Operation ................................................................................................... 225
7-23
Control Register Settings for One-Shot Pulse Output with Software Trigger ............................................... 226
7-24
Timing of One-Shot Pulse Output Operation with Software Trigger ............................................................. 227
7-25
Control Register Settings for One-Shot Pulse Output with External Trigger ................................................ 228
7-26
Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) ................ 229
7-27
Start Timing of 16-Bit Timer Register n ........................................................................................................ 230
7-28
Timing After Changing Compare Register During Timer Count Operation................................................... 230
7-29
Data Hold Timing of Capture Register.......................................................................................................... 231
7-30
Operation Timing of OVFn Bit ...................................................................................................................... 232
7-31
Block Diagram of TM2 to TM7...................................................................................................................... 235
7-32
Timing of Interval Timer Operation ............................................................................................................... 242
LIST OF FIGURES (2/6)
Title
User's Manual U13850EJ6V0UD
Page
21

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