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After reset: 00H
7
TCLn0
0
(n = 4, 5)
After reset: 00H
7
TCLn1
0
(n = 4, 5)
TCLn3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note
Only in the V850/SB1.
Cautions 1. When TCLn0 and TCLn1 are overwritten by different data, write after temporarily
stopping the timer.
2. Always set bits 3 to 7 of TCLn0 and bits 1 to 7 of TCLn1 to 0.
Remark
When connected in cascade, the settings of TCL53 to TCL50 of TM5 are invalid.
238
CHAPTER 7
TIMER/COUNTER FUNCTION
R/W
Address: FFFFF264H, FFFFF274H
6
5
4
0
0
0
R/W
Address: FFFFF26EH, FFFFF27EH
6
5
4
0
0
0
TCLn2
TCLn1
TCLn0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
User's Manual U13850EJ6V0UD
3
2
0
TCLn2
3
2
0
0
Count clock selection
Count clock
20 MHz
−
TIn falling edge
−
TIn rising edge
f
/4
200 ns
XX
f
/8
400 ns
XX
f
/16
800 ns
XX
1.6 µ s
f
/32
XX
6.4 µ s
f
/128
XX
30.5 µ s
f
(Subclock)
XT
−
Setting prohibited
−
Setting prohibited
3.2 µ s
f
/64
XX
12.8 µ s
f
/256
XX
−
Setting prohibited
−
Setting prohibited
−
Setting prohibited
−
Setting prohibited
1
0
TCLn1
TCLn0
1
0
0
TCLn3
f
XX
Note
12.58 MHz
−
−
318 ns
636 ns
1.3 µ s
2.5 µ s
10.2 µ s
30.5 µ s
−
−
5.1 µ s
20.3 µ s
−
−
−
−
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