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(9) IEBus interrupt status register (ISR)
This register indicates the status when IEBus issues an interrupt. The ISR is read to generate an interrupt,
after which the specified interrupt processing is carried out.
Reset the ISR register after reading it. Until it is reset, the INTIE2 interrupt signal is not generated (nor held
pending).
To reset the ISR register, reset each flag, satisfying the reset conditions in Table 19-8.
Table 19-8. Reset Conditions of Flags in ISR Register
Flag Name
IEERR, STARTF, STATUSF
ENDTRNS, ENDFRAM
Caution Even if 0 is written to the ENDTRNS or ENDFRAM flag by accessing the ISR register, these
flags are not reset. Reset them as described above.
Remark
MSTRQ:
ENSLVTX: Bit 4 of the IEBus control register (BCR)
ENSLVRX: Bit 3 of the IEBus control register (BCR)
CHAPTER 19
IEBus CONTROLLER (V850/SB2)
Reset Condition
Byte write operation of ISR register. Any value
can be written.
Set MSTRQ, ENSLVTX, or ENSLVRX flag.
Bit 6 of the IEBus control register (BCR)
User's Manual U13850EJ6V0UD
Processing Example
ISR = 00H, etc.
BCR register = 88H or ENSLVTX
= 1, etc.
575
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