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(c) One-shot pulse output
The one-shot pulse output operates correctly only in free-running mode or in clear & start mode at the valid
edge of the TIn0 pin. The one-shot pulse cannot be output in the clear & start mode on a match of TMn and
CRn0 because an overflow does not occur.
(10) Capture operation
(a) If the valid edge of TIn0 is specified for the count clock
When the valid edge of TIn0 is specified for the count clock, the capture register with TIn0 specified as a
trigger will not operate correctly.
(b) If both rising and falling edges are selected as valid edge of TIn0
If the CRn0 register capture trigger is set to the inverse phase of the valid edge of TIn0 and both the rising
and falling edges are selected as the valid edge of TIn0, a capture operation is not performed.
(c) To capture the signals correctly from TIn0 and TIn1
The capture trigger needs a pulse longer than twice the count clock selected by prescaler mode registers n0
and n1 (PRMn0, PRMn1) in order to correctly capture the signals from TIn1 and TIn0.
(d) Interrupt request input
Although a capture operation is performed a the falling edge of the count clock, interrupt request inputs
(INTTMn0, INTTMn1) are generated at the rising edge of the next count clock.
(11) Compare operation
(a) When rewriting CRn0 and CRn1 during timer operation
When rewriting 16-bit timer capture/compare registers n0 and n1 (CRn0, CRn1), if the value is close to or
larger than the timer value, the match interrupt request generation or clear operation may not be performed
correctly.
(b) When CRn0 and CRn1 are set to compare mode
When CRn0 and CRn1 are set to compare mode, they do not perform a capture operation even if a capture
trigger is input.
(12) Edge detection
(a) When the TIn0 or TIn1 pin is high level immediately after a system reset
When the TIn0 or TIn1 pin is high level immediately after a system reset, if the valid edge of the TIn0 or TIn1
pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n
(TMn) is then enabled, the rising edge will be detected immediately. Care is therefore needed when the TIn0
or TIn1 pin is pulled up. However, when operation is enabled after being stopped, the rising or falling edge
is not detected.
(b) Sampling clock for noise elimination
The sampling clock for noise elimination differs depending on whether the TIn0 valid edge is used as a count
clock or a capture trigger. The former is sampled by f
selected using prescaler mode registers n0 or n1 (PRMn0, PRMn1). Detecting the valid edge can eliminate
short pulse width noise because a capture operation is performed only after the valid edge is sampled and a
valid level is detected twice.
CHAPTER 7
TIMER/COUNTER FUNCTION
User's Manual U13850EJ6V0UD
/2, and the latter is sampled by the count clock
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