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(4) Block diagram (Port 0)
WR
PU
RD
WR
PORT
Output latch
WR
PM
Remarks 1. PU0: Pull-up resistor option register 0
PM0: Port 0 mode register
RD:
Port 0 read signal
WR:
Port 0 write signal
2. n = 0 to 7
478
CHAPTER 14
Figure 14-1. Block Diagram of P00 to P07
PU0
PU0n
Selector
(P0n)
PM0
PM0n
User's Manual U13850EJ6V0UD
PORT FUNCTION
V
DD
P-ch
P00/NMI
P01/INTP0
P02/INTP1
P03/INTP2
P04/INTP3
P05/INTP4/ADTRG
P06/INTP5/RTPTRG
P07/INTP6
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