Bus Timing; Memory Read - NEC V850/SB1 User Manual

4.8 Bus Timing

The V850/SB1 and V850/SB2 can execute read/write control for an external device using the following two modes.
• Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals
• Mode using RD, WRL, WRH, and ASTB signals
Set these modes by using the BIC bit of the system control register (SYC) (see 4.2.2 (1) System control register
(SYC)).
CLKOUT (output)
A16 to A21 (output)
A1 to A15 (output)
AD0 to AD15 (I/O)
WRH, WRL (output)
DSTB, RD (output)
UBEN, LBEN (output)
Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken line indicates the high-impedance state.
CHAPTER 4 BUS CONTROL FUNCTION
Figure 4-8. Memory Read (1/4)
Address
ASTB (output)
R/W (output)
H
WAIT (input)
User's Manual U13850EJ6V0UD
(a) 0 waits
T1 T2
Address
Address
Data
T3
137