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1.3.5 Function blocks (V850/SB1 (B versions))
(1) Internal block diagram
NMI
INTC
INTP0 to INTP6
TI00,TI01,
TI10,TI11
Timer/counter
TO0,TO1
16-bit timer:
TM0, TM1
TI2/TO2
8-bit timer:
TI3/TO3
TM2 to TM7
TI4/TO4
TI5/TO5
SIO
SO0
CSI0/I
Note 3
SI0/SDA0
Note 4
Note 3
SCK0/SCL0
SO2
CSI2/I
Note 3
SI2/SDA1
Note 4
Note 3
SCK2/SCL1
SO1/TXD0
SI1/RXD0
CSI1/UART0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
CSI3/UART1
SCK3/ASCK1
SO4
Variable
SI4
length CSI4
SCK4
Key return
KR0 to KR7
DMAC: 6 ch
Watch timer
Watchdog
timer
µ PD703031B, 703031BY:
Notes 1.
µ PD703033B, 703033BY:
µ PD703030B, 703030BY:
µ PD703032B, 703032BY:
µ PD70F3033B, 70F3033BY: 256 K (flash memory)
µ PD70F3030B, 70F3030BY: 384 K (flash memory)
µ PD70F3032B, 70F3032BY: 512 K (flash memory)
µ PD703031B, 703031BY:
2.
µ PD703033B, 703033BY, 70F3033B, 70F3033BY:
µ PD703030B, 703030BY, 703032B, 703032BY,:
70F3030B, 70F3030BY, 70F3032B, 70F3032BY
SDA0, SDA1, SCL0, and SCL1 pins are available only in the µ PD703030BY, 703031BY, 703032BY,
3.
703033BY, 70F3032BY, 70F3030BY, and 70F3033BY
C function is available only in the µ PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY,
2
4.
I
70F3032BY, and 70F3033BY
µ PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY
5.
µ PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY
6.
CHAPTER 1
ROM
Note
1
32-bit barrel
RAM
General-purpose
Note
32 bits × 32
2
2
C0
2
C1
128 KB (mask ROM)
256 KB (mask ROM)
384 K (mask ROM)
512 K (mask ROM)
User's Manual U13850EJ6V0UD
INTRODUCTION
CPU
ROM
correction
PC
Multiplier
shifter
16 ×16→32
System
register
ALU
registers
Ports
RTP
3.3 V
8 KB
16 KB
24 KB
HLDRQ (P96)
Instruction
HLDAK (P95)
queue
ASTB (P94)
DSTB/RD (P93)
R/W /WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
BCU
WAIT (P110)
A1 to A12
(P100 to P107,
P110 to P113)
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
CLKOUT
A/D
X1
converter
X2
CG
XT1
XT2
RESET
Regulator
V
DD
V
SS
BV
DD
BV
SS
EV
DD
EV
SS
Note 5
V
PP
Note 6
IC
49
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