Fmc Connector Jtag Bypass; Clock Generation - Xilinx KCU105 User Manual

The Digilent USB module, Xilinx platform USB cable interface header (J3), and the system
IMPORTANT:
controller (U111) bank 34 JTAG interface cannot be operated simultaneously. Make sure that only one
JTAG configuration interface is selected.

FMC Connector JTAG Bypass

When an FMC mezzanine card is attached to the KCU105 board, it is automatically added to
the JTAG chain through electronically controlled single-pole single-throw (SPST) switches
U26 (HPC) and U27 (LPC). The SPST switches are in a normally closed state and transition to
an open state when an FMC mezzanine card is attached. Switch U26 adds an attached HPC
FMC mezzanine card to the FPGAs JTAG chain as determined by the
FMC_HPC_PRSNT_M2C_B signal (active low). Switch U27 adds an attached LPC FMC
mezzanine card to the FPGAs JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B
signal (active low). The attached FMC card must implement a TDI-to-TDO connection via a
device or bypass jumper to ensure that the JTAG chain connects to the FPGA U1.
The JTAG connectivity on the KCU105 board allows a host computer to download bitstreams
to the FPGA using the Vivado design tools. In addition, the JTAG connector allows debug
tools such as the Vivado serial I/O analyzer or a software debugger to access the FPGA. The
Vivado design tools can also be used to program the dual Quad-SPI Flash memory.

Clock Generation

[Figure 1-2, callout 6]
The KCU105 evaluation board provides nine clock sources for the XCKU040 device. The
KCU105 board clocking system is illustrated in
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
Figure 1-9.
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