Usb 3.0 Transceiver And Usb 2.0 Ulpi Phy - Xilinx ZCU111 User Manual

Table 3-12: IP4856CX25 U107 Adapter Pin-Out (Cont'd)
Aires Adapter Pin
Number
16
17
18
19
20
21
22
23
24
25
The connections between the SD NXP IP4856CX25 (U107) level-shifter and the XCZU28DR
RFSoC PS bank 501 are referenced in
USB0 (MIO 52-63)
The USB interface on the PS-side serves multiple roles as a host or device controller. The
USB 3.0 interface is supported by the RFSoC GTR interface while the USB 2.0 capabilities of
the SMSC USB3320C controller are shared on a common USB 3.0 micro USB type A
connector (J96).

USB 3.0 Transceiver and USB 2.0 ULPI PHY

[Figure 2-1, callout 5]
The ZCU111 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI
transceiver at U12 to support a USB connection to the host computer (see
USB cable is supplied in the ZCU111 evaluation kit (standard-A connector to host computer,
USB 3.0 A connector to ZCU111 board connector J96). The USB3320 is a high-speed USB 2.0
PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard
defines the interface between the USB controller IP and the PHY device, which drives the
physical USB bus. Using the ULPI standard reduces the interface pin count between the USB
controller IP and the PHY device.
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
IP4856CX25 U107 Pin
Number
E1
E3
A1
E5
D5
C5
D4
B5
A5
C2
Appendix B, Xilinx Design
www.xilinx.com
Chapter 3: Board Component Descriptions
IP4856CX25 U107 Pin
Name
DATA1_H
DIR_1_3
DATA2_H
DATA1_SD
DATA0_SD
CLK_SD
CMD_SD
DATA3_SD
DATA2_SD
ENABLE
Constraints.
Figure 3-8). A
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