Nested Vectored Interrupt Controller (Nvic); Table 44. Nvic Register Summary - ST STM32F4 Series Programming Manual

PM0214
4.3

Nested vectored interrupt controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it
uses. The NVIC supports:
•
Up to 81 interrupts (interrupt number depends on the STM32 device type; refer to the
datasheets)
•
A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority
• Level and pulse detection of interrupt signals
•
Dynamic reprioritization of interrupts
• Grouping of priority values into group priority and subpriority fields
•
Interrupt tail-chaining
• An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
Address Name
0xE000E100- NVIC_ISER0-
0xE000E10B NVIC_ISER2
0XE000E180- NVIC_ICER0-
0xE000E18B NVIC_ICER2
0XE000E200- NVIC_ISPR0-
0xE000E20B NVIC_ISPR2
0XE000E280- NVIC_ICPR0-
0xE000E29C NVIC_ICPR2
0xE000E300- NVIC_IABR0-
0xE000E31C NVIC_IABR2
0xE000E400- NVIC_IPR0-
0xE000E503 NVIC_IPR20
0xE000EF00 STIR

Table 44. NVIC register summary

Required
Type Reset value
privilege
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
WO Configurable 0x00000000
DocID022708 Rev 6
Description
Table 4.3.2: Interrupt set-enable registers
(NVIC_ISERx) on page 209
Table 4.3.3: Interrupt clear-enable registers
(NVIC_ICERx) on page 210
Table 4.3.4: Interrupt set-pending registers
(NVIC_ISPRx) on page 211
Table 4.3.5: Interrupt clear-pending registers
(NVIC_ICPRx) on page 212
Table 4.3.6: Interrupt active bit registers
(NVIC_IABRx) on page 213
Table 4.3.7: Interrupt priority registers
(NVIC_IPRx) on page 214
Table 4.3.8: Software trigger interrupt register
(NVIC_STIR) on page 215
Core peripherals
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