Interrupt Priority Registers (Nvic_Iprx); Table 46. Ipr Bit Assignments; Figure 19. Nvic_Iprx Register Mapping - ST STM32F4 Series Programming Manual

Core peripherals
4.3.7

Interrupt priority registers (NVIC_IPRx)

Address offset: 0x00- 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
The NVIC_IPR0-IPR80 registers provide an 8-bit priority field for each interrupt. These
registers are byte-accessible. Each register holds four priority fields, that map to four
elements in the CMSIS interrupt priority array IP[0] to IP[67], as shown in
Bits
[31:24]
[23:16]
[15:8]
[7:0]
See Interrupt set-enable registers (NVIC_ISERx) on page 209
the interrupt priority array, that provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt N as follows:
•
The corresponding IPR number, M, is given by M = N DIV 4
•
The byte offset of the required Priority field in this register is N MOD 4, where:
–
–
–
–
214/260

Figure 19. NVIC_IPRx register mapping

31
IPR20
Reserved
IP[4m+ 3]
IPR
IP[3]
IPR0

Table 46. IPR bit assignments

Name
Priority, byte offset 3
Each priority field holds a priority value, 0-255. The lower the value,
Priority, byte offset 2
the greater the priority of the corresponding interrupt. The processor
implements only bits[7:4] of each field, bits[3:0] read as zero and
Priority, byte offset 1
ignore writes.
Priority, byte offset 0
byte offset 0 refers to register bits[7:0]
byte offset 1 refers to register bits[15:8]
byte offset 2 refers to register bits[23:16]
byte offset 3 refers to register bits[31:24].
DocID022708 Rev 6
24 23 16 15
Reserved
IP[4m+ 2]
IP[2]
Figure
8 7
IP[80]
Reserved
IP[4m+ 1] IP[4m]
IP[1] IP[0]
Function
for more information about
PM0214
19.
0