Clz - ST STM32F4 Series Programming Manual

The STM32 Cortex-M4 instruction set
Operation
ASR, LSL, LSR, and ROR move the bits in the Rm register to the left or right by the number
of places specified by constant n or register Rs.
RRX moves the bits in Rm register to the right by 1.
In all these instructions, the result is written to Rd, but the value in Rm register remains
unchanged. For details on what result is generated by the different instructions see
operations on page
Restrictions
Do not use either SP or PC.
Condition flags
If S is specified:
•
These instructions update the N and Z flags according to the result
•
The C flag is updated to the last bit shifted out, except when the shift length is 0 (see
Shift operations on page
Examples
ASR R7, R8, #9
LSLS R1, R2, #3
LSR R4, R5, #6
ROR R4, R5, R6
RRX R4, R5
3.5.4

CLZ

Count leading zeros.
Syntax
CLZ{cond} Rd, Rm
Where:
•
'cond' is an optional condition code (see
•
'Rd' is the destination register.
•
'Rm' is the operand register.
Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the
result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31]
is set.
Restrictions
Do not use either SP or PC.
Condition flags
This instruction does not change the flags.
86/260
61.
61).
; arithmetic shift right by 9 bits
; logical shift left by 3 bits with flag update
; logical shift right by 6 bits
; rotate right by the value in the bottom byte of R6
; rotate right with extend
DocID022708 Rev 6
Conditional execution on page
PM0214
Shift
64).