Memory Management Fault Address Register (Mmfsr) - ST STM32F4 Series Programming Manual

PM0214
4.4.13

Memory management fault address register (MMFSR)

Bit 7 MMARVALID: Memory Management Fault Address Register (MMAR) valid flag. If a memory
management fault occurs and is escalated to a hard fault because of priority, the hard fault
handler must set this bit to 0. This prevents problems on return to a stacked active memory
management fault handler whose MMAR value is overwritten.
0: Value in MMAR is not a valid fault address
1: MMAR holds a valid fault address.
Bit 6 Reserved, must be kept cleared
Bit 5 MLSPERR:
0: No MemManage fault occurred during floating-point lazy state preservation
1: A MemManage fault occurred during floating-point lazy state preservation
Bit 4 MSTKERR: Memory manager fault on stacking for exception entry. When this bit is 1, the SP
is still adjusted but the values in the context area on the stack might be incorrect. The
processor has not written a fault address to the MMAR.
0: No stacking fault
1: Stacking for an exception entry has caused one or more access violations.
Bit 3 MUNSTKERR: Memory manager fault on unstacking for a return from exception. This fault is
chained to the handler. This means that when this bit is 1, the original return stack is still
present. The processor has not adjusted the SP from the failing return, and has not performed
a new save. The processor has not written a fault address to the MMAR.
0: No unstacking fault
1: Unstack for an exception return has caused one or more access violations.
Bit 2 Reserved, must be kept cleared
Bit 1 DACCVIOL: Data access violation flag. When this bit is 1, the PC value stacked for the
exception return points to the faulting instruction. The processor has loaded the MMAR with
the address of the attempted access.
0: No data access violation fault
1: The processor attempted a load or store at a location that does not permit the operation.
Bit 1 IACCVIOL: Instruction access violation flag. This fault occurs on any access to an XN region,
even the MPU is disabled or not present.
When this bit is 1, the PC value stacked for the exception return points to the faulting
instruction. The processor has not written a fault address to the MMAR.
0: No instruction access violation fault
1: The processor attempted an instruction fetch from a location that does not permit
execution.
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