Umull, Umlal, Smull, And Smlal - ST STM32F4 Series Programming Manual

The STM32 Cortex-M4 instruction set
SMULBB
SMULTT
SMULTB
SMULWT
SMULWB
3.6.11

UMULL, UMLAL, SMULL, and SMLAL

Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and
producing a 64-bit result.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
Where:
•
op' is one of:
UMULL: Unsigned long multiply.
UMLAL: Unsigned long multiply, with accumulate.
SMULL: Signed long multiply.
SMLAL: Signed long multiply, with accumulate.
•
'cond' is an optional condition code (see
• 'RdHi, RdLo' are the destination registers. For UMLAL and SMLAL they also hold the
accumulating value.
•
'Rn', 'Rm' are registers holding the operands
Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It
multiplies these integers and places the least significant 32 bits of the result in RdLo, and
the most significant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It
multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in
RdHi and RdLo, and writes the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two's complement signed
integers. It multiplies these integers and places the least significant 32 bits of the result in
RdLo, and the most significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two's complement signed
integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer
contained in RdHi and RdLo, and writes the result back to RdHi and RdLo.
122/260
R0, R4, R5 ; Multiplies the bottom halfword of R4 with the bottom
; halfword of R5, multiplies results and writes to R0
R0, R4, R5 ; Multiplies the top halfword of R4 with the top
; halfword of R5, multiplies results and writes to R0
R0, R4, R5 ; Multiplies the top halfword of R4 with the bottom
; halfword of R5, multiplies results and writes to R0
R4, R5, R3 ; Multiplies R5 with the top halfword of R3,
; extracts top 32 bits and writes to R4
R4, R5, R3 ; Multiplies R5 with the bottom halfword of R3,
; extracts top 32 bits and writes to R4.
DocID022708 Rev 6
Conditional execution on page
PM0214
64)