ST STM32F4 Series Programming Manual page 50

The STM32 Cortex-M4 instruction set
Mnemonic
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
CBZ
CLREX
CLZ
CMN
CMP
CPSID
CPSIE
DMB
DSB
EOR, EORS {Rd,} Rn, Op2
ISB
IT
LDM
LDMDB,
LDMEA
LDMFD,
LDMIA
LDR
LDRB,
LDRBT
LDRD
LDREX
50/260
Table 20. Cortex-M4 instructions (continued)
Operands
{Rd,} Rn, Op2 Logical AND
Rd, Rm, <Rs|#n> Arithmetic shift right
label Branch
Rd, #lsb, #width Bit field clear
Rd, Rn, #lsb, #width Bit field insert
{Rd,} Rn, Op2 Bit clear
#imm Breakpoint
label Branch with link
Rm Branch indirect with link
Rm Branch indirect
Compare and branch if non
Rn, label
zero
Rn, label Compare and branch if zero
— Clear exclusive
Rd, Rm Count leading zeros
Rn, Op2 Compare negative
Rn, Op2 Compare
Change processor state,
iflags
disable interrupts
Change processor state,
iflags
enable interrupts
— Data memory barrier
— Data synchronization barrier
Exclusive OR
Instruction synchronization
—
barrier
— If-then condition block
Load multiple registers,
Rn{!}, reglist
increment after
Load multiple registers,
Rn{!}, reglist
decrement before
Load multiple registers,
Rn{!}, reglist
increment after
Rt, [Rn, #offset] Load register with word
Rt, [Rn, #offset] Load register with byte
Rt, Rt2, [Rn, #offset] Load register with two bytes
Rt, [Rn, #offset] Load register exclusive
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N,Z,C 3.5.2 on page 84
N,Z,C 3.5.3 on page 85
— 3.9.5 on page 141
— 3.9.1 on page 138
— 3.9.1 on page 138
N,Z,C 3.5.2 on page 84
— 3.11.1 on page 180
— 3.9.5 on page 141
— 3.9.5 on page 141
— 3.9.5 on page 141
— 3.9.6 on page 143
— 3.9.6 on page 143
— 3.4.9 on page 79
— 3.5.4 on page 86
N,Z,C,V 3.5.5 on page 87
N,Z,C,V 3.5.5 on page 87
— 3.11.2 on page 181
— 3.11.2 on page 181
— 3.11.4 on page 183
— 3.11.4 on page 183
N,Z,C 3.5.2 on page 84
— 3.11.5 on page 184
— 3.9.7 on page 144
— 3.4.6 on page 75
— 3.4.6 on page 75
— 3.4.6 on page 75
— 3.4 on page 68
— 3.4 on page 68
— 3.4.2 on page 70
— 3.4.8 on page 78