ST STM32F4 Series Programming Manual page 52

The STM32 Cortex-M4 instruction set
Mnemonic
QDADD
QDSUB
QSAX
QSUB
QSUB16
QSUB8
RBIT
REV
REV16
REVSH
ROR, RORS Rd, Rm, <Rs|#n>
RRX, RRXS
RSB, RSBS
SADD16
SADD8
SASX
SBC, SBCS
SBFX
SDIV
SEV
SHADD16
SHADD8
SHASX
SHSAX
SHSUB16
SHSUB8
SMLABB,
SMLABT,
SMLATB,
SMLATT
SMLAD,
SMLADX
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Table 20. Cortex-M4 instructions (continued)
Operands
{Rd,} Rn, Rm Saturating add
Saturating double and
{Rd,} Rn, Rm
subtract
Saturating subtract and add
{Rd,} Rn, Rm
with exchange
{Rd,} Rn, Rm Saturating subtract
{Rd,} Rn, Rm Saturating subtract 16
{Rd,} Rn, Rm Saturating subtract 8
Rd, Rn Reverse bits
Rd, Rn Reverse byte order in a word
Reverse byte order in each
Rd, Rn
halfword
Reverse byte order in bottom
Rd, Rn
halfword and sign extend
Rotate right
Rd, Rm Rotate right with extend
{Rd,} Rn, Op2 Reverse subtract
{Rd,} Rn, Rm Signed add 16
{Rd,} Rn, Rm Signed add 8
Signed add and subtract with
{Rd,} Rn, Rm
exchange
{Rd,} Rn, Op2 Subtract with carry
Rd, Rn, #lsb, #width Signed bit field extract
{Rd,} Rn, Rm Signed divide
— Send event
{Rd,} Rn, Rm Signed halving add 16
{Rd,} Rn, Rm Signed halving add 8
Signed halving add and
{Rd,} Rn, Rm
subtract with exchange
Signed halving subtract and
{Rd,} Rn, Rm
add with exchange
{Rd,} Rn, Rm Signed halving subtract 16
{Rd,} Rn, Rm Signed halving subtract 8
Signed multiply accumulate
Rd, Rn, Rm, Ra long
(halfwords)
Signed multiply accumulate
Rd, Rn, Rm, Ra
dual
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3.7.5 on page 129
3.7.5 on page 129
3.7.4 on page 128
3.7.3 on page 127
3.7.4 on page 128
3.7.4 on page 128
— 3.7.4 on page 128
— 3.5.8 on page 91
— 3.5.8 on page 91
— 3.5.8 on page 91
N,Z,C 3.5.3 on page 85
N,Z,C 3.5.3 on page 85
N,Z,C,V 3.5.1 on page 82
3.5.9 on page 92
3.5.9 on page 92
3.5.14 on page 97
N,Z,C,V 3.5.1 on page 82
— 3.9.2 on page 139
— 3.6.3 on page 111
— 3.11.9 on page 188
— 3.5.10 on page 93
— 3.5.10 on page 93
— 3.5.11 on page 94
— 3.5.11 on page 94
— 3.5.12 on page 95
— 3.5.12 on page 95
Q 3.6.3 on page 111
Q 3.6.4 on page 113