ST STM32F4 Series Programming Manual page 244

Core peripherals
Offset Register
SHPR3
0x20
Reset Value
SHCRS
0x24
Reset Value
CFSR
0x28
Reset Value
HFSR
0x2C
Reset Value
MMAR
0x34
Reset Value
BFAR
0x38
Reset Value
AFSR
0x3C
Reset Value
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Table 52. SCB register map and reset values (continued)
PRI15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
UFSR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
DocID022708 Rev 6
PRI14
0 0 0 0 0 0 0 0 0
BFSR
Reserved
MMAR[31:0]
BFAR[31:0]
IMPDEF[31:0]
PM0214
Reserved
0 0 0 0 0
MMFSR
0