Table 6. Epsr Bit Definitions - ST STM32F4 Series Programming Manual

The Cortex-M4 processor
Bits
Bits 31:27
Bits 26:25, 15:10
Bits 26:25, 15:10
Bits 23:16
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application
software are ignored. Fault handlers can examine EPSR value in the stacked PSR to
indicate the operation that is at fault. See
page 41.
Interruptible-continuable instructions
When an interrupt occurs during the execution of an LDM STM, PUSH, POP, VLDM, VSTM,
VPUSH, or VPOP instruction, the processor:
•
Stops the load multiple or store multiple instruction operation temporarily
•
Stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
•
Returns to the register pointed to by bits[15:12]
•
Resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
If-Then block
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each
instruction in the block is conditional. The conditions for the instructions are either all the
same, or some can be the inverse of others. See
Thumb state
The Cortex-M4 processor only supports execution of instructions in Thumb state. The
following can clear the T bit to 0:
•
Instructions BLX, BX and POP{PC}
•
Restoration from the stacked xPSR value on an exception return
• Bit[0] of the vector value on an exception entry or reset
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See
on page 46
Exception mask registers
The exception mask registers disable the handling of exceptions by the processor. Disable
exceptions where they might impact on timing critical tasks.
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Table 6. EPSR bit definitions

Reserved.
ICI: Interruptible-continuable instruction bits, see
instructions on page
IT: Indicates the execution state bits of the IT instruction, see
Bit 24 T: Thumb state bit.
Reserved.
Bits 9:0 Reserved.
for more information.
DocID022708 Rev 6
Description
22.
Section 2.3.7: Exception entry and return on
IT on page 144
PM0214
Interruptible-continuable
IT on page 144
for more information.
Lockup
.