System Handler Priority Registers (Shprx); Table 51. System Fault Handler Priority Fields - ST STM32F4 Series Programming Manual

Core peripherals
4.4.8

System handler priority registers (SHPRx)

The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that
have configurable priority.
SHPR1-SHPR3 are byte accessible.
The system fault handlers and the priority field and register for each handler are:
Memory management fault
Bus fault
Usage fault
SVCall
PendSV
SysTick
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field,
and bits[3:0] read as zero and ignore writes (where M=4).
System handler priority register 1 (
Address offset: 0x18
Reset value: 0x0000 0000
Required privilege: Privileged
31 30 29 28
15 14 13 12
PRI_5[7:4]
rw rw rw rw
Bits 31:24 Reserved, must be kept cleared
Bits 23:16 PRI_6: Priority of system handler 6, usage fault
Bits 15:8 PRI_5: Priority of system handler 5, bus fault
PRI_4: Priority of system handler 4, memory management fault
Bits 7:0
System handler priority register 2 (SHPR2)
Address offset: 0x1C
Reset value: 0x0000 0000
Required privilege: Privileged
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Table 51. System fault handler priority fields

Handler
PRI_4
PRI_5
PRI_6
PRI_11
PRI_14
PRI_15
27 26 25
Reserved
11 10 9
PRI_5[3:0]
r r r
DocID022708 Rev 6
Field
System handler priority register 1 (SHPR1)
System handler priority register 2 (SHPR2) on
page 232
System handler priority register 3 (SHPR3) on
page 233
SHPR1
)
24 23 22 21
PRI_6[7:4]
rw rw rw
8 7 6
PRI_4[7:4]
r rw rw rw
Register description
20 19 18
PRI_6[3:0]
rw r r
5 4 3 2
PRI_4[7:4]
rw r r
PM0214
17 16
r r
1 0
r r