Interrupt Active Bit Registers (Nvic_Iabrx) - ST STM32F4 Series Programming Manual

PM0214
4.3.6

Interrupt active bit registers (NVIC_IABRx)

Address offset: 0x00- 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
The IABR0-IABR2 registers indicate which interrupts are active.
The bit assignments are:
31 30 29 28
r r r
15 14 13 12
r r r
Bits 31:0 ACTIVE: Interrupt active flags
A bit reads as 1 if the status of the corresponding interrupt is active or active and pending.
27 26 25
r r r r
11 10 9
r r r r
0: Interrupt not active
1: Interrupt active
DocID022708 Rev 6
24 23 22 21
ACTIVE[31:16]
r r r r
8 7 6 5
ACTIVE[15:0]
r r r r
Core peripherals
20 19 18 17
r r r r
4 3 2 1
r r r r
16
r
0
r
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