ST STM32F4 Series Programming Manual page 65

Cortex-m4
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PM0214
Conditional execution is available by using conditional branches or by adding condition code
suffixes to instructions. See
suffixes to add to instructions to make them conditional instructions. The condition code
suffix enables the processor to test a condition based on the flags. If the condition test of a
conditional instruction fails, the instruction:
Does not execute.
Does not write any value to its destination register.
Does not affect any of the flags.
Does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-then
instruction block. See
IT instruction. Depending on the vendor, the assembler might automatically insert an IT
instruction if you have conditional instructions outside the IT block.
Use the CBZ and CBNZ instructions to compare the value of a register against zero and
branch on the result.
This section describes:
The condition flags
Condition code suffixes on page 66
The condition flags
The APSR contains the following condition flags:
N: Set to 1 when the result of the operation is negative, otherwise cleared to 0.
Z: Set to 1 when the result of the operation is zero, otherwise cleared to 0.
C: Set to 1 when the operation results in a carry, otherwise cleared to 0.
V: Set to 1 when the operation causes an overflow, otherwise cleared to 0.
For more information about the APSR see
A carry occurs:
If the result of an addition is greater than or equal to 2
If the result of a subtraction is positive or zero.
As the result of an inline barrel shifter operation in a move or logical instruction.
Overflow occurs if the sign of a result does not match the sign of the result had the operation
been performed at infinite precision, for example:
if adding two negative values results in a positive value.
if adding two positive values results in a negative value.
if subtracting a positive value from a negative value generates a positive value.
if subtracting a negative value from a positive value generates a negative value.
The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except
that the result is discarded. See the instruction descriptions for more information.
Most instructions update the status flags only if the S suffix is specified. See the instruction
descriptions for more information.
Table 23: Condition code suffixes on page 66
IT on page 144
for more information and restrictions when using the
Program status register on page
DocID022708 Rev 6
The STM32 Cortex-M4 instruction set
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