Smuad And Smusd - ST STM32F4 Series Programming Manual

The STM32 Cortex-M4 instruction set
3.6.9

SMUAD and SMUSD

Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax
op{X}{cond} Rd, Rn, Rm
Where:
• op is one of:
SMUAD: Signed dual multiply add.
SMUADX: Signed dual multiply add reversed.
SMUSD: Signed dual multiply subtract.
SMUSDX: Signed dual multiply subtract reversed.
–
•
'cond' is an optional condition code (see
•
'Rd' is the destination register.
•
'Rn', 'Rm' are registers holding the first and second operands
Operation
SMUAD interprets first and second operand values as two signed halfwords:
1. Optionally rotates the halfwords of the second operand.
2. Performs two signed 16 × 16-bit multiplications.
3. Adds the two multiplication results together.
4. Writes the result of the addition to the destination register.
SMUSD interprets the values from the first and second operands as two's complement
signed integers:
1. Optionally rotates the halfwords of the second operand.
2. Performs two signed 16 × 16-bit multiplications.
3. Subtracts the result of the top halfword multiplication from the result of the bottom
halfword multiplication.
4. Writes the result of the subtraction to the destination register.
Restrictions
In these instructions: Do not use either SP or PC.
Condition flags
Sets the Q flag if the addition overflows. The multiplications cannot overflow.
Examples
SMUAD
SMUADX
120/260
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
R0, R4, R5 ; Multiplies bottom halfword of R4 with the bottom
; halfword of R5, adds multiplication of top halfword
; of R4 with top halfword of R5, writes to R0
R3, R7, R4 ; Multiplies bottom halfword of R7 with top halfword
; of R4, adds multiplication of top halfword of R7
; with bottom halfword of R4, writes to R3
DocID022708 Rev 6
Conditional execution on page
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