Hard Fault Status Register (Hfsr) - ST STM32F4 Series Programming Manual

Core peripherals
4.4.14

Hard fault status register (HFSR)

Address offset: 0x2C
Reset value: 0x0000 0000
Required privilege: Privileged
The HFSR gives information about events that activate the hard fault handler. This register
is read, write to clear. This means that bits in the register read normally, but writing 1 to any
bit clears that bit to 0.
31 30 29 28
DEBU FORC
G_VT ED
rc_w1 rc_w1
15 14 13 12
Bit 31 DEBUG_VT: Reserved for Debug use. When writing to the register you must write 0 to this bit,
otherwise behavior is unpredictable.
Bit 30 FORCED: Forced hard fault. Indicates a forced hard fault, generated by escalation of a fault
with configurable priority that cannot be handles, either because of priority or because it is
disabled.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find
the cause of the fault.
Bits 29:2 Reserved, must be kept cleared
VECTTBL: Vector table hard fault. Indicates a bus fault on a vector table read during
Bit 1
exception processing. This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that was preempted by the exception.
Bit 0 Reserved, must be kept cleared
240/260
27 26 25
11 10 9
Reserved
0: No forced hard fault
1: Forced hard fault.
0: No bus fault on vector table read
1: Bus fault on vector table read.
24 23 22
Reserved
8 7 6
DocID022708 Rev 6
21 20 19 18
5 4 3 2
PM0214
17 16
1 0
VECT
TBL
Res.
rc_w1