Exception Handlers - ST STM32F4 Series Programming Manual

The Cortex-M4 processor
Table 16. Properties of the different exception types (continued)
Exception IRQ
(1)
number number
15 -1
16 and 0 and
above above
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other
than interrupts. The IPSR returns the Exception number. For further information see
page 21.
2. See Vector table on page 39
3. See System handler priority registers (SHPRx) on page
4. See Interrupt priority registers (NVIC_IPRx) on page
5. Increasing in steps of 4.
For an asynchronous exception other than reset, the processor can execute another
instruction between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that
configurable priority. For further information, see:
•
System handler control and state register (SHCSR) on page 234
•
Interrupt clear-enable registers (NVIC_ICERx) on page 210
For more information about hard faults, memory management faults, bus faults, and usage
faults, see
2.3.3

Exception handlers

The processor handles exceptions using:
Interrupt Service
Routines (ISRs)
Fault handlers
System handlers
38/260
Exception
(1)
type
SysTick
Interrupt (IRQ)
for more information.
Section 2.4: Fault handling on page
Interrupts IRQ0 to IRQ81 are the exceptions handled by ISRs.
Hard fault, memory management fault, usage fault, bus fault are fault
exceptions handled by the fault handlers.
NMI, PendSV, SVCall SysTick, and the fault exceptions are all
system exceptions that are handled by system handlers.
DocID022708 Rev 6
Vector address
Priority
or offset
(3)
Configurable 0x0000003C
0x00000040 and
(4)
Configurable
(5)
above
232.
214.
Table 16 on page 37
43.
Activation
(2)
Asynchronous
Asynchronous
Interrupt program status register on
shows as having
PM0214