Figure 12. Cortex-M4 Stack Frame Layout - ST STM32F4 Series Programming Manual

The Cortex-M4 processor
stack frame is the same as that of ARMv7-M implementations without an FPU.
page 42
Exception frame with
floating-point storage
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The alignment of the stack frame is controlled via the STKALIGN bit of the Configuration
Control Register (CCR).
The stack frame includes the return address. This is the address of the next instruction in
the interrupted program. This value is restored to the PC at exception return so that the
interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the
exception handler start address from the vector table. When stacking is complete, the
processor starts executing the exception handler. At the same time, the processor writes an
EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack
frame and what operation mode the was processor was in before the entry occurred.
If no higher priority exception occurs during exception entry, the processor starts executing
the exception handler and automatically changes the status of the corresponding pending
interrupt to active.
If another higher priority exception occurs during exception entry, the processor starts
executing the exception handler for this exception and does not change the pending status
of the earlier exception. This is the late arrival case.
42/260
also shows this stack frame.

Figure 12. Cortex-M4 stack frame layout

...
Pre-IRQ top of stack
{aligner}
FPSCR
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Decreasing
PSR
memory
PC
address
LR
R12
R3
R2
R1
R0
IRQ top of stack
DocID022708 Rev 6
...
{aligner}
PSR
PC
LR
R12
R3
R2
R1
R0
Exception frame without
floating-point storage
PM0214
Figure 12 on
Pre-IRQ top of stack
IRQ top of stack
MS30019V1