Nvic Design Hints And Tips; Table 47. Cmsis Functions For Nvic Control - ST STM32F4 Series Programming Manual

PM0214
4.3.10

NVIC design hints and tips

Ensure software uses correctly aligned register accesses. The processor does not support
unaligned accesses to NVIC registers. See the individual register descriptions for the
supported access sizes.
An interrupt can enter pending state even it is disabled. Disabling an interrupt only prevents
the processor from taking that interrupt.
Before programming VTOR to relocate the vector table, ensure the vector table entries of
the new vector table are setup for fault handlers, NMI and all enabled exception like
interrupts. For more information see
page 226.
NVIC programming hints
Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The
CMSIS provides the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
void NVIC_EnableIRQ(IRQn_t IRQn)
void NVIC_DisableIRQ(IRQn_t IRQn)
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
void NVIC_SetPendingIRQ (IRQn_t IRQn)
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
uint32_t NVIC_GetActive (IRQn_t IRQn)
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_t IRQn)
void NVIC_SystemReset (void)
The input parameter IRQn is the IRQ number, see
exception types on page
documentation.

Table 47. CMSIS functions for NVIC control

CMSIS interrupt control function
37. For more information about these functions see the CMSIS
DocID022708 Rev 6
Section 4.4.4: Vector table offset register (VTOR) on
Set the priority grouping
Enable IRQn
Disable IRQn
Return true (IRQ-Number) if IRQn is
pending
Set IRQn pending
Clear IRQn pending status
Return the IRQ number of the active
interrupt
Set priority for IRQn
Read priority of IRQn
Reset the system
Table 16: Properties of the different
Core peripherals
Description
217/260
259