Interrupt Control And State Register (Icsr) - ST STM32F4 Series Programming Manual

Core peripherals
4.4.3

Interrupt control and state register (ICSR)

Address offset: 0x04
Reset value: 0x0000 0000
Required privilege: Privileged
The ICSR:
•
Provides:
–
–
• Indicates:
–
–
–
–
Caution: When you write to the ICSR, the effect is unpredictable if you:
•
Write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
•
Write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
31 30 29 28
Reserved
rw rw
15 14 13 12
VECTPENDING[3:0]
r r r
Bit 31 NMIPENDSET: NMI set-pending bit.
Write:
Read:
Because NMI is the highest-priority exception, normally the processor enter the NMI
exception handler as soon as it registers a write of 1 to this bit, and entering the handler clears
this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
Bits 30:29 Reserved
224/260
A set-pending bit for the Non-Maskable Interrupt (NMI) exception
Set-pending and clear-pending bits for the PendSV and SysTick exceptions
The exception number of the exception being processed
Whether there are preempted active exceptions
The exception number of the highest priority pending exception
Whether any interrupts are pending.
27 26 25
w rw w
11 10 9
Reserved
r r
0: No effect
1: Change NMI exception state to pending.
0: NMI exception is not pending
1: NMI exception is pending
DocID022708 Rev 6
24 23 22 21
Reserved
r
8 7 6 5
VECTACTIVE[8:0]
rw rw rw rw
20 19 18
VECTPENDING[6:4]
Reserved
r
4 3 2
rw rw rw
PM0214
17 16
r r
1 0
rw rw