Ldrex And Strex - ST STM32F4 Series Programming Manual

The STM32 Cortex-M4 instruction set
3.4.8

LDREX and STREX

Load and Store Register Exclusive.
Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
Where:
•
'cond' is an optional condition code (see
•
'Rd' is the destination register for the returned status.
•
'Rt' is the register to load or store.
•
'Rn' is the register on which the memory address is based.
•
'offset' is an optional offset applied to the value in Rn. If offset is omitted, the address is
the value in Rn.
Operation
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a
memory address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to
a memory address. The address used in any store-exclusive instruction must be the same
as the address in the most recently executed load-exclusive instruction. The value stored by
the store-exclusive instruction must also have the same data size as the value loaded by the
preceding load-exclusive instruction. This means software must always use a load-
exclusive instruction and a matching store-exclusive instruction to perform a
synchronization operation, see
If a store-exclusive instruction performs the store, it writes 0 to its destination register.
If it does not perform the store, it writes 1 to its destination register.
If the store-exclusive instruction writes 0 to the destination register, it is guaranteed that no
other process in the system has accessed the memory location between the load-exclusive
and store-exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding load-
exclusive and store-exclusive instruction to a minimum.
Note: The result of executing a store-exclusive instruction to an address that is different from that
used in the preceding load-exclusive instruction is unpredictable.
78/260
Conditional execution on page
Synchronization primitives on page
DocID022708 Rev 6
PM0214
64).
33.