Nested Vectored Interrupt Controller (Nvic); Table 45. Nvic Register Summary - ST STM32F3 Series Programming Manual

Core peripherals
4.3

Nested vectored interrupt controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it
uses. The NVIC supports:
•
Up to 240 interrupts
•
A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority
•
Level and pulse detection of interrupt signals
•
Dynamic reprioritization of interrupts
•
Grouping of priority values into group priority and subpriority fields
•
Interrupt tail-chaining
•
An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
Address Name
0xE000E100- NVIC_ISER0-
0xE000E11F NVIC_ISER7
0XE000E180- NVIC_ICER0-
0xE000E19F NVIC_ICER7
0XE000E200- NVIC_ISPR0-
0xE000E21F NVIC_ISPR7
0XE000E280- NVIC_ICPR0-
0xE000E29F NVIC_ICPR7
0xE000E300- NVIC_IABR0-
0xE000E31F NVIC_IABR7
0xE000E400- NVIC_IPR0-
0xE000E4EF NVIC_IPR59
0xE000EF00 STIR
Note: The number of interrupts is product-dependent. Refer to reference manual/datasheet of
relevant STM32 product for related information.
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Table 45. NVIC register summary

Required
Type Reset value
privilege
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
RW Privileged 0x00000000
WO Configurable 0x00000000
PM0214 Rev 10
Description
Table 4.3.2: Interrupt set-enable register x
(NVIC_ISERx) on page 210
Table 4.3.3: Interrupt clear-enable register x
(NVIC_ICERx) on page 211
Table 4.3.4: Interrupt set-pending register x
(NVIC_ISPRx) on page 212
Table 4.3.5: Interrupt clear-pending register x
(NVIC_ICPRx) on page 213
Table 4.3.6: Interrupt active bit register x
(NVIC_IABRx) on page 214
Table 4.3.7: Interrupt priority register x
(NVIC_IPRx) on page 215
Table 4.3.8: Software trigger interrupt register
(NVIC_STIR) on page 216
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