ST STM32F4 Series Programming Manual page 53

PM0214
Mnemonic
SMLAL
SMLALBB,
SMLALBT,
SMLALTB,
SMLALTT
SMLALD,
SMLALDX
SMLAWB,
SMLAWT
SMLSD
SMLSLD
SMMLA
SMMLS,
SMMLR
SMMUL,
SMMULR
SMUAD
SMULBB,
SMULBT
SMULTB,
SMULTT
SMULL
SSAT
SSAT16
SSAX
SSUB16
SSUB8
STM
STMDB,
STMEA
STMFD,
STMIA
STR
STRB,
STRBT
Table 20. Cortex-M4 instructions (continued)
Operands
Signed multiply with
RdLo, RdHi, Rn, Rm accumulate (32 x 32 + 64), 64-
bit result
Signed multiply accumulate
RdLo, RdHi, Rn, Rm long,
halfwords
Signed multiply accumulate
RdLo, RdHi, Rn, Rm
long dual
Signed multiply accumulate,
Rd, Rn, Rm, Ra
word by halfword
Rd, Rn, Rm, Ra Signed multiply subtract dual
Signed multiply subtract long
RdLo, RdHi, Rn, Rm
dual
Signed most significant word
Rd, Rn, Rm, Ra
multiply accumulate
Signed most significant word
Rd, Rn, Rm, Ra
multiply subtract
Signed most significant word
{Rd,} Rn, Rm
multiply
{Rd,} Rn, Rm Signed dual multiply add
{Rd,} Rn, Rm Signed multiply (halfwords)
Signed multiply (32 x 32), 64-
RdLo, RdHi, Rn, Rm
bit result
Rd, #n, Rm {,shift #s} Signed saturate
Rd, #n, Rm Signed saturate 16
Signed subtract and add with
{Rd,} Rn, Rm
exchange
{Rd,} Rn, Rm Signed subtract 16
{Rd,} Rn, Rm Signed subtract 8
Store multiple registers,
Rn{!}, reglist
increment after
Store multiple registers,
Rn{!}, reglist
decrement before
Store multiple registers,
Rn{!}, reglist
increment after
Rt, [Rn, #offset] Store register word
Rt, [Rn, #offset] Store register byte
DocID022708 Rev 6
The STM32 Cortex-M4 instruction set
Brief description Flags Page
— 3.6.2 on page 110
— 3.6.5 on page 114
— 3.6.5 on page 114
Q 3.6.3 on page 111
Q 3.6.6 on page 116
— 3.6.6 on page 116
— 3.6.7 on page 118
— 3.6.7 on page 118
— 3.6.8 on page 119
Q 3.6.9 on page 120
— 3.6.10 on page 121
— 3.6.2 on page 110
Q 3.7.1 on page 125
Q 3.7.2 on page 126
GE 3.5.14 on page 97
— 3.5.13 on page 96
— 3.5.13 on page 96
— 3.4.6 on page 75
— 3.4.6 on page 75
— 3.4.6 on page 75
— 3.4 on page 68
— 3.4 on page 68
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