Isb - ST STM32F4 Series Programming Manual

The STM32 Cortex-M4 instruction set
3.11.5

ISB

Instruction synchronization barrier.
Syntax
ISB{cond}
Where: 'cond' is an optional condition code, see
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so
that all instructions following the ISB are fetched from cache or memory again, after the ISB
instruction is completed.
Condition flags
This instruction does not change the flags.
Examples
ISB
184/260
; Instruction Synchronisation Barrier
DocID022708 Rev 6
Conditional execution on page
PM0214
64.