Table 37. Memory Attributes Summary - ST STM32F4 Series Programming Manual

PM0214
When memory regions overlap, a memory access is affected by the attributes of the region
with the highest number. For example, the attributes for region 7 take precedence over the
attributes of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory
map, but is accessible from privileged software only.
The Cortex-M4 MPU memory map is unified. This means instruction accesses and data
accesses have same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor
generates a memory management fault. This causes a fault exception, and might cause
termination of the process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on
the process to be executed. Typically, an embedded OS uses the MPU for memory
protection.
Configuration of MPU regions is based on memory types, see
regions, types and attributes on page
Table 37
Memory type
Strongly-ordered -
Device
Normal
shows the possible MPU region attributes.

Table 37. Memory attributes summary

Shareability
-
Shared -
Non-shared -
Non-cacheable
Shared Write-through Cacheable
Write-back Cacheable
Non-cacheable
Non-shared Write-through Cacheable
Write-back Cacheable
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28.
Other attributes
All accesses to Strongly-ordered
memory occur in program order. All
Strongly-ordered regions are assumed
to be shared.
Memory-mapped peripherals that
several processors share.
Memory-mapped peripherals that only a
single processor uses.
Normal memory that is shared between
several processors.
Normal memory that only a single
processor uses.
Core peripherals
Section 2.2.1: Memory
Description
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