Behavior Of Memory Accesses; Table 12. Memory Access Behavior - ST STM32F4 Series Programming Manual

PM0214
2.2.3

Behavior of memory accesses

The behavior of accesses to each region in the memory map is:
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xED000000-
0xED0FFFFF
0xED100000-
0xFFFFFFFF
1. See Memory regions, types and attributes on page 28
The Code, SRAM, and external RAM regions can hold programs. However, it is
recommended that programs always use the Code region. The reason of this is that the
processor has separate buses that enable instruction fetches and data accesses to occur
simultaneously.
The MPU can override the default memory access behavior described in this section. For
more information, see
Instruction prefetch and branch prediction
The Cortex-M4 processor:
•
Prefetches instructions ahead of execution
•
Speculatively prefetches from branch target addresses.

Table 12. Memory access behavior

Memory Memory
region type
(1)
Code Normal
(1)
SRAM Normal
(1)
Peripheral Device
External
(1)
Normal
RAM
External
(1)
Device
device
Private
Strongly-
Peripheral
(1)
ordered
Bus
Memory
(1)
mapped Device
peripherals
Memory protection unit (MPU) on page
DocID022708 Rev 6
XN
Executable region for program code. Can also put
-
data here.
Executable region for data. Can also put code
here.
-
This region includes bit band and bit band alias
areas, see Table 13 on page
This region includes bit band and bit band alias
(1)
XN
areas, see Table 14 on page
- Executable region for data.
(1)
XN External Device memory
This region includes the NVIC, system timer, and
(1)
XN
system control block.
This region includes all the STM32 standard
(1)
XN
peripherals.
for more information.
The Cortex-M4 processor
Description
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31.
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