Shift Operations; Figure 13. Asr #3 - ST STM32F4 Series Programming Manual

PM0214
3.3.4

Shift operations

Register shift operations move the bits in a register left or right by a specified number of bits,
the shift length. Register shift can be performed:
•
Directly by the instructions ASR, LSR, LSL, ROR, and RRX. The result is written to a
destination register.
•
During the calculation of operand2 by the instructions that specify the second operand
as a register with shift (see
the instruction.
The permitted shift lengths depend on the shift type and the instruction (see the individual
instruction description or
Register shift operations update the carry flag except when the specified shift length is 0.
The following sub-sections describe the various shift operations and how they affect the
carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is
the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the Rm register to the right by
n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the
register into the left-hand n bits of the result (see
You can use the ASR #n operation to divide the value in the Rm register by 2
result being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated
to the last bit shifted out, bit[n-1], of the Rm register.
Note: 1 If n is 32 or more, all the bits in the result are set to the value of bit[31] of Rm.
2 If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
31
Flexible second operand on page
Flexible second operand). If the shift length is 0, no shift occurs.

Figure 13. ASR #3

DocID022708 Rev 6
The STM32 Cortex-M4 instruction set
59). The result is used by
Figure 13: ASR #3 on page
5 4 3 2 1
61).
n
, with the
Carry
Flag
0
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