Floating-Point Context Address Register (Fpcar); Floating-Point Status Control Register (Fpscr) - ST STM32F4 Series Programming Manual

Core peripherals
4.6.3

Floating-point context address register (FPCAR)

Address offset: 0x08
Reset value: 0x0000000
Required privilege: Privileged
The FPCAR register holds the location of the unpopulated floating-point register space
allocated on an exception stack frame.
31 30 29 28
15 14 13 12
Bits 31:3 ADDRESS: Location of unpopulated floating-point register space allocated on an exception
stack frame.
Bits 2:0 Reserved. Read as Zero, Writes Ignored.
4.6.4

Floating-point status control register (FPSCR)

Address offset: Not mapped
Reset value: 0x0000000
Required privilege: Privileged
The FPSCR register provides all necessary user level control of the floating-point system.
31 30 29 28
N Z C
rw rw rw rw
15 14 13 12
Bit 31 N: Negative condition code flag. Floating-point comparison operations update these flags. For
more details on the result, refer to
0: Operation result was positive, zero, greater than, or equal.
1: Operation result was negative or less than.
Bit 30 Z: Zero condition code flag. Floating-point comparison operations update these flags. For more
details on the result, refer to
0: Operation result was not zero.
1: Operation result was zero.
Bit 29 C: Carry condition code flag. Floating-point comparison operations update these flags. For more
details on the result, refer to
0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit.
1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
254/260
27 26 25
11 10 9
ADDRESS[15:3]
rw
27 26 25
V AHP DN
Reserv
ed
rw rw
11 10 9
Reserved
24 23 22
ADDRESS[31:16]
rw
8 7 6
24 23 22
FZ RMode
rw rw rw
8 7 6
IDC
Reserved
rw
Table 56.
Table 56.
Table 56.
DocID022708 Rev 6
21 20 19 18
5 4 3 2
21 20 19 18
Reserved
5 4 3 2
IXC UFC OFC
rw rw rw
PM0214
17 16
1 0
Reserved
17 16
1 0
DZC IOC
rw rw