Interrupt Clear-Pending Registers (Nvic_Icprx) - ST STM32F4 Series Programming Manual

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Core peripherals
4.3.5

Interrupt clear-pending registers (NVIC_ICPRx)

Address offset: 0x00 - 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
The ICPR0-ICPR2 registers remove the pending state from interrupts, and show which
interrupts are pending.
31
30
29
28
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:0 CLRPEND: Interrupt clear-pending bits
Write:
0: No effect
1: Removes the pending state of an interrupt
Read:
0: Interrupt is not pending
1: Interrupt is pending
Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
212/260
27
26
25
24
CLRPEND[31:16]
rc_w1
rc_w1
rc_w1
rc_w1
11
10
9
8
CLRPEND[15:0]
rc_w1
rc_w1
rc_w1
rc_w1
DocID022708 Rev 6
23
22
21
20
rc_w1
rc_w1
rc_w1
rc_w1
7
6
5
rc_w1
rc_w1
rc_w1
rc_w1
19
18
17
rc_w1
rc_w1
rc_w1
4
3
2
1
rc_w1
rc_w1
rc_w1
PM0214
16
rc_w1
0
rc_w1

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