Interrupt Set-Enable Registers (Nvic_Iserx) - ST STM32F4 Series Programming Manual

PM0214
4.3.2

Interrupt set-enable registers (NVIC_ISERx)

Address offset: 0x00 - 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
31 30 29 28
rs rs rs rs
15 14 13 12
rs rs rs rs
Bits 31:0 SETENA: Interrupt set-enable bits.
Write:
Read:
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending,
but the NVIC never activates the interrupt, regardless of its priority.
27 26 25
rs rs rs
11 10 9
rs rs rs
0: No effect
1: Enable interrupt
0: Interrupt disabled
1: Interrupt enabled.
24 23 22
SETENA[31:16]
rs rs rs
8 7 6
SETENA[15:0]
rs rs rs
DocID022708 Rev 6
Core peripherals
21 20 19 18
rs rs rs rs
5 4 3 2
rs rs rs rs
17 16
rs rs
1 0
rs rs
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